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The capabilities of any given computer or computing system are never sufficient to solve all classes of problems efficiently and economically. There will always be a demand for faster arithmetic speed as well as for larger and faster memory. In fact, by 1955 the scientific computing facilities at the Ballistic Research Laboratory, APG, became unable to adequately support Ordnance requirements in the area of ballistic computations. The improved version of EDVAC and ORDVAC were laboring on a round-the-clock basis. The computer improvement programs which expanded the capability of these computers turned out to be only stop-gap measures. The existing machines were unable to adequately support the more than 100 active problems then being solved in the pursuit of ballistics research and the computation of firing tables and ballistic data for conventional artillery, rockets, and guided missiles. ENIAC was not able to keep up with EDVAC or ORDVAC and was no longer used after 2 October 1955. This placed the entire computation load on EDVAC and ORDVAC each of which operated 168 hours per week, with but a short time off each day for trouble shooting, repair, and improvements. Troubles over problem priority began to occur. Day-time computer runs were limited to twenty-minute program checks. Scramble time was a brief period of a few minutes for squeezing in a few high priority problems out of scheduled order. It was obvious that additional computer capacity was badly needed and this in the form of a computing machine that would be far superior to the existing machines.
The state of the art had advanced by 1957 to the point where superior machines were being developed by IBM, Sperry Rand, the Universities of Illinois and California, the Massachusetts Institute of Technology, and the National Bureau of Standards. Other companies and universities were also making rapid progress in the development and production of computing and data processing systems.
The decision was made to support the work of the National Bureau of Standards in exchange for the results of their development program and (in 1957) $50,000 of Ordnance R&D funds were transferred to the National Bureau of Standards to assist in the development of universal logical packages which could be used in the construction of a new, fast, reliable, scientific computing machine. At that time the National Bureau of Standards was committed to the design of their new PILOT Multi-Computer System. The Ordnance funds assisted the Bureau of Standards in arriving at a tentative design of arithmetic, logical, and control units. The design and samples of the logical packages were provided to the Ballistic Research Laboratory at Aberdeen Proving Ground. Tests conducted at BRL showed that improvements in the design of the package were necessary. These modifications were approved by the Bureau of Standards and the sum of $175,000 was transferred in February 1958, to the National Bureau of Standards to cover the cost of 6,000 of the packages to be ordered along with the Bureau's requirement for its PILOT Multi-Computer System. At the same time the programming staff of the Computing Laboratory at BRL prepared a description of the instructions to be automatically executed by the new computing machine. Due to the different types of application, the desire for easy programming and for reasons of economy, the Ballistic Research Laboratory at APG and the National Bureau of Standards parted ways in development. All that remained in common were the logical package and certain aspects of the high-speed arithmetic unit, which used the high-speed carry logic as proposed by the Bureau. The instruction code, physical construction, internal arrangement, control logic, peripheral equipment, and many other aspects differed. The logical design, physical design, and layout of the system was done independently by Computing Laboratory personnel at BRL.
The construction of plug-in units and racks was done under contract by the Technitrol Engineering Company of Philadelphia, PA. The development of the high-speed storage element was performed by Ampex Computer Products, Incorporated, of Culver City, CA (formerly Telemeter Magnetics, Inc.). The contract, approved by the Chief of Ordnance, called for the delivery of a 4,096-word storage unit with a cycle time of less than two microseconds. The operational unit, after some delays due to technical difficulties, was delivered to BRL on 15 May 1961 under Ordnance Contract No. DA-04-495-ORD-1500 at a total cost of $680,000. Certain other components were also obtained under contract from various companies.
The assembly and logical wiring of the system was performed by Computing Laboratory personnel at BRL. This staff of computer engineers and programmers also conducted the checkout and testing of the system.
The new computing machine was named BRLESC, Ballistic Research Laboratory's Electronic Scientific Computer. It was designed by Ordnance personnel, for Ordnance Corps use, although in every respect it is a general purpose, high-speed, automatic computer. Its approximate ultimate cost is estimated at two million dollars. BRLESC was scheduled to be in operation by the end of 1961.
The BRLESC is an general purpose, electronic, digital computer with parallel arithmetic mode and synchronous timing. It was designed primarily for the solution of scientific problems in which high computational speed and high precision are required. As the descriptive phrase "general purpose" implies, the machine may be programmed to perform any task which is amenable to numerical methods of solution.
The applications of BRLESC are as follows:
1. Exterior ballistics problems such as high altitude, solar and lunar trajectories, computation for the preparation of firing tables and guidance control data for Ordnance weapons, including free flight and guided missiles.
2. Interior ballistic problems, including projectile, propellant, and launcher behavior, e.g., physical characteristics of solid propellants, equilibrium composition, and thermodynamic properties of rocket propellants, computation of detonation waves for reflected shock waves, vibration of gun barrels and the flow of fluids in porous media.
3. Terminal ballistic problems, including nuclear, fragmentation, and penetration effects in such areas as explosion kinetics, shaped charge behavior, ignition, and heat transfer.
4. Ballistic measurement problems, including photogrammetric, ionospheric, and damping of satellite spin calculations, reduction of satellite doppler tracking data, and computation of satellite orbital elements.
5. Weapon systems evaluation problems, including antiaircraft and antimissile evaluation, war game problems, linear programming for solution of Army logistical problems, probabilities of mine detonations, and lethal area and kill probabilities of mine detonations, and lethal area and kill probability studies of missiles.
The binary number system is used exclusively in the arithmetic unit of the machine. The input-output routines (programs) automatically convert decimal input information into binary form and, conversely, convert binary numbers into decimal form for output. The arithmetic unit is constructed of standard vacuum tube logical packages, with tube driven, crystal diode logical gating. It contains 1,727 vacuum tubes of 4 types, 853 transistors of 3 types, 46,500 diodes of 2 types, and 1,600 pulse transformers of 1 type. Logical events are controlled by a five-phase megacycle clock, permitting decisions at the rate of five million per second.
The storage system of the machine consists of a high-speed magnetic core memory of 4,096 words. Each word is 72 bits long, which is equivalent computationally to approximately 19 decimal digits, since 4 parity bits and 4 sign bits are not included in the operands. The complete read-write cycle time of this memory is 1.5 microseconds. Additional high-speed storage will be added to the machine when funds become available. Also, magnetic drum storage units will be installed as back-up memory. The capacity of these drums is to be about 35,000 words.
The input-output devices of the machine are capable of reading cards, punching cards, reading magnetic tape, and recording on magnetic tape. A maximum of 16 magnetic tape handlers may be installed on line, that is, they are directly accessible to the programmer. Any two magnetic tape handlers, one drum, the card reader, and the card punch may be operated simultaneously under separate automatic controls. Arithmetic processing may occur concurrently with input-output operations. This means that information is processed automatically as it becomes available from an input device and automatic interlocks are built into the machine to insure that the proper information is available.
Information may be transferred to or from the machine by means of punched cards or magnetic tape. All information must be coded in a binary manner since the machine (as most modern computers) can only handle 0's and 1's, that is, hole or no hole, or magnetization in one direction or the other. The binary number system is used because of the binary nature of most of the devices used in the construction of the machine. The internal workings of the machine are simpler if only pure binary numbers and instructions are used. However, programmed routines can be designed to process any kind of information. The actual information may be a pure binary number, a binary coded decimal number, a binary coded alphabetic character, or literally any type of information the programmer desires. An output routine will arrange this information in the proper format for punched card output if desired, or for magnetic tape output. The punched cards may be tabulated on conventional punched card equipment and the magnetic tapes may be ready by special converter equipment which operates into a high-speed printer at rates up to 1,500 lines per minute, with 160 characters per line.
BRLESC was designed so that a maximum of concurrent operations can take place whenever possible. A "look-ahead of instructions, words, and indices" feature is incorporated to allow the machine to operate most effectively with a memory which cycles in one microsecond. Also, many special instructions may be executed while the arithmetic unit is working on an arithmetic instruction. In addition, all five input-output trunks may be operating simultaneously.
The control of BRLESC consists of many units, each controlling their associated process, but all regulated by a master control center, which has a pre-determined time priority system and which prohibits the initiation of new events in any of the various concurrent trunks should there be some conflict in the use of information or units. For example, if two tape trunks are to use the same tape handler for different purposes at the same time, the trunk which receives the first request gets priority to use the handler and the other trunk must wait until the first has finished using the handler. Also, should a program want to use information that has not arrived yet from one of five input-output trunks the master control center recognizes the problem and causes the program to wait until the information is delivered. The master control also recognizes manual commands from a console and then relays the commands to the respective sub-unit.
Magnetic tape speeds operate at an effective rate of 120,000 six-bit characters per second. Search through magnetic tape in the forward or backward direction by large blocks of information is an incorporated feature. New programs can be located rapidly through the use of file markers. Drum transfer rates are 130,000 seventy-two-bit words per second.
BRLESC is provided with a parity system to check word transfers as they pass through the memory and to or from tapes and drums. The master control unit is altered in the event a non-parity condition occurs.
The computer is designed to operate on an internally stored program of detailed instructions. This feature is the single, most important reason for the tremendous growth of the computer industry, because it makes computers truly flexible and easy to use. Since instructions are in numerical form, arithmetic operations may be performed on them, that is they may be manipulated in the arithmetic unit. In this way the program can modify its own instructions during the course of the computation in response to conditions that develop. This allows the programmer to exercise his ingenuity and gives him latitude to do many things without writing a great many detailed instructions.
Another very valuable feature is that the machine can change address in instructions by fixed amounts automatically. This feature is called indexing and permits the programmer to use the same set of instructions to process as much data as he desires simply by changing the index value instead of modifying the basic instructions.
Code checking features will include stopping on any selected address, the display of the contents of any memory cell, the display of normal or abnormal conditions, the ability to manually store in any selected memory cell, and the ability to transfer control to any part of the system. Parity checking is performed in each of the four 17-bit groups in each word.
It is believed that BRLESC will be a significant contribution to the Ordnance Corps and to the scientific community, because it will permit the solution of problems never before possible due to the excessive amount of time required; and it will solve these problems at a precision which was possible on earlier machines only by complicated, time-consuming methods. (See Appendix IV for technical data of BRLESC.)